1. Field of the Invention
The present invention relates in general to the field of electronics, and more specifically to a system and method for voltage conversion using a switching power converter with efficient switching control signal period generation.
2. Description of the Related Art
Many devices utilize electrical power to operate. Power is initially supplied by a power source, such as a public utility company, and power sources generally provide a steady state input voltage. However, the voltage levels utilized by various devices may differ from the steady state input voltage provided by the power source. For example, light emitting diode (LED) based lighting systems, typically operate from voltage levels that differ from voltage level supplied by a public utility company. To accommodate the difference between the voltage from the power source and the voltage utilized by the device, power converters are connected between the power source and the device to convert a supply voltage level from an alternating current (AC) power source to, for example, another AC power source having a voltage level different than the supply voltage level. Power converters can also convert AC power into direct (DC) power and DC power into AC power.
Switching power converters represent one example of a type of power converter. A switching power converter utilizes switching and energy storage technology to convert an input voltage into an output voltage suitable for use by a particular device connected to the switching power converter.
FIG. 1 depicts a power control system 100, which includes a switching power converter 102. Voltage source 101 supplies an AC input “mains” voltage Vmains to a full, diode bridge rectifier 103. The voltage source 101 is, for example, a public utility, and the AC mains voltage Vmains is, for example, a 60 Hz/120 V mains voltage in the United States of America or a 50 Hz/230 V mains voltage in Europe. The rectifier 103 rectifies the input mains voltage Vmains. The rectifier 103 rectifies the input mains voltage Vmains and supplies a rectified, time-varying, primary supply voltage VX to the switching power converter. The switching power converter 102 provides approximately constant voltage power to load 112 while maintaining a resistive input characteristic to voltage source 101. Providing approximately constant voltage power to load 112 while maintaining an approximately resistive input characteristic to voltage source 101 is referred to as power factor correction (PFC). Thus, a power factor corrected switching power converter 102 is controlled so that an input current iL to the switching power converter 102 varies in approximate proportion to the AC mains voltage Vmains.
PFC and output voltage controller 114 controls the conductivity of PFC switch 108 so as to provide power factor correction and to regulate the output voltage VC of switching power converter 102. The PFC and output voltage controller 114 attempts to control the inductor current iL so that the average inductor current iL is linearly and directly proportional to the primary supply voltage VX. A proportionality constant relates the inductor current iL to the primary supply voltage VX, and the proportionality constant is adjusted to regulate the voltage to load 112. The PFC and output voltage controller 114 supplies a pulse width modulated (PWM) switch control signal CS0 to control the conductivity of switch 108. In at least one embodiment, switch 108 is a field effect transistor (FET), and switch control signal CS0 is the gate voltage of switch 108. The values of the pulse width and duty cycle of switch control signal CS0 depend on at least two signals, namely, the primary supply voltage VX and the capacitor voltage/output voltage VC. Output voltage VC is also commonly referred to as a “link voltage”. Current control loop 119 provides current iRTN to PFC and output voltage controller 114 to allow PFC and output voltage controller 114 to adjust an average iL current 210 (FIG. 2) to equal a target iL current 208 (FIG. 2).
Capacitor 106 supplies stored energy to load 112 when diode 111 is reverse biased and when the primary supply voltage VX is below the RMS value of the input mains. The value of capacitor 106 is a matter of design choice and, in at least one embodiment, is sufficiently large so as to maintain a substantially constant output voltage VC, as established by a PFC and output voltage controller 114. A typical value for capacitor 106, when used with a 400 V output voltage VC, is 1 microfarad per watt of maximum output power supplied via switching power converter 102. The output voltage VC remains at a substantially constant target value during constant load conditions with ripple at the frequency of primary supply voltage VX. However, as load conditions change, the output voltage VC changes. The PFC and output voltage controller 114 responds to the changes in voltage VC by adjusting the switch control signal CS0 to return the output voltage VC to the target value. In at least one embodiment, the PFC and output voltage controller 114 includes a small capacitor 115 to filter any high frequency signals from the primary supply voltage VX.
The switching power converter 102 incurs switching losses each time switch 108 switches between nonconductive and conductive states due to parasitic impedances. The parasitic impedances include a parasitic capacitance 132 across switch 108. During each period TT of switching switch control signal CS0, energy is used to, for example, charge parasitic capacitance 132. Thus, switching power converter 102 incurs switching losses during each period TT of switch control signal CS0.
PFC and output voltage controller 114 controls switching power converter 102 so that a desired amount of power is transferred to capacitor 106. The desired amount of power depends upon the voltage and current requirements of load 112. An input voltage control loop 116 provides a sample of primary supply voltage VX to PFC and output voltage controller 114. PFC and output voltage controller 114 determines a difference between a reference voltage VREF, which indicates a target voltage for output voltage VC, and the actual output voltage VC sensed from node 122 and received as feedback from voltage loop 118. The PFC and output voltage controller 114 generally utilizes technology, such as proportional integral (PI) compensation control, to respond to differences in the output voltage VC relative to the reference voltage VREF. The PFC and output voltage controller 114 processes the differences to smoothly adjust the output voltage VC to avoid causing rapid fluctuations in the output voltage VC in response to small error signals. The PFC and output voltage controller 114 generates a pulse width modulated switch control signal CS0 that drives switch 108. Prodić, Compensator Design and Stability Assessmentfor Fast Voltage Loops of Power Factor Correction Rectifiers, IEEE Transactions on Power Electronics, Vol. 12, No. 5, September 1007, pp. 1719-1729 (referred to herein as “Prodić”), describes an example of PFC and output voltage controller 114.
FIGS. 2 and 3 depict respective switching control strategies utilized by typical switching power converters, such as switching power converter 102, to convert the input voltage VX into a power factor corrected output voltage VC. FIG. 2 depicts a transition switching strategy, and FIG. 3 depicts a constant period switching strategy. Referring to FIGS. 1 and 2, PFC and output voltage controller 114 controls the conductivity of PFC switch 108. The primary supply voltage VX 202 is, in at least one embodiment, a rectified sine wave. To regulate the amount of power transferred and maintain a power factor close to one, PFC and output voltage controller 114 varies the period TT of switch control signal CS0 so that the inductor current iL (also referred to as the ‘input current’) tracks changes in primary supply voltage VX and holds the output voltage VC constant. The transition switching strategy 204 illustrates that, as the primary supply voltage VX increases, PFC and output voltage controller 114 increases the period TT of switch control signal CS0. As the primary supply voltage VX decreases, PFC and output voltage controller 114 decreases the period of switch control signal CS0. In one embodiment of transition switching strategy 204, the pulse width time T1 is approximately constant.
Time T2 represents the flyback time of inductor 110 that occurs when switch 108 is nonconductive and the diode 111 is conductive. In at least one embodiment, the value of inductor 110 is a matter of design choice. In at least one embodiment, the value of inductor 110 is chosen to store sufficient power transferred from voltage source 101 when switch 108 conducts in order to transfer power to capacitor 106 when switch 108 is non-conductive to maintain a desired output voltage VC. For the transition switching strategy 204, the pulse width time T1 plus the flyback time T2 equals the period TT of switch control signal CS0.
The inductor current iL waveform 206 depicts the general behavior of inductor current iL over time relative to the primary supply voltage VX. The inductor current iL ramps ‘up’ during pulse width T1 when the switch 108 conducts, i.e. is “ON”. The inductor current iL ramps down during flyback time T2 when switch 108 is nonconductive, i.e. is “OFF”, and supplies inductor current iL through diode 111 to recharge capacitor 106. Discontinuous conduction mode (DCM) occurs when the inductor current iL reaches 0 during the period TT of switch control signal CS0. Continuous conduction mode (CCM) occurs when the inductor current iL is greater than 0 during the entire period TT. Transition switching strategy 204 operates switching power converter 102 at the boundary of DCM and CCM by beginning each period of switch control signal CS0 when the inductor current iL just equals 0. The frequency 1/TT of switch control signal CS0 is, for example, between 20 kHz and 130 kHz. The period TT of switch control signal CS0 and, thus, the duration of each cycle of inductor iL depicted in inductor current iL waveform 206 is exaggerated for visual clarity. Transition switching strategy 204 operates the switch 108 at high frequencies when little power is transferred from voltage source 101, such as near the zero crossing 212 of the mains voltage Vmains and at light load, i.e. when the power demand of load 112 is light.
The PFC and output voltage controller 114 sets a target current 208 that tracks the primary supply voltage VX. When the inductor current iL reaches the target current 208 during the pulse width T1, the switch control signal CS0 opens switch 108, and inductor current iL decreases to zero during flyback time T2. The average current 210 represents the average inductor current iL. The average inductor current iL tracks the primary supply voltage VX, thus, providing power factor correction.
Referring to FIG. 3, the constant period switching strategy 302 maintains a constant period TT of switch control signal CS0 and varies the pulse width T1 of switch control signal CS0 to control inductor current iL. As the primary supply voltage VX increases from 0 to line peak, PFC and output voltage controller 114 decreases the pulse width T1 of switch control signal CS0. Constant period switching strategy 302 operates switching power converter 102 in DCM so that the flyback time T2 plus the pulse width T1 is less than or equal to the period TT of switch control signal CS0. Inductor current iL waveform 304 depicts the effects of the constant period switching strategy 302 on the inductor current iL relative to the primary supply voltage VX. As with the transition switching strategy 204, for the constant period switching strategy 302, the PFC and output voltage controller 114 sets a target current 208 that tracks the primary supply voltage VX. For constant period strategy 302, TT≧(T1+T2), so switching power converter 102 operates in DCM.
PFC and output voltage controller 114 updates the switch control signal CS0 at a frequency much greater than the frequency of input voltage VX. The frequency of input voltage VX is generally 50-60 Hz. The frequency 1/TT of switch control signal CS0 is, for example, between 10 kHz and 130 kHz. Frequencies at or above 20 kHz avoid audio frequencies and frequencies at or below 130 kHz avoids significant switching inefficiencies.
The constant period switching strategy 302 is not efficient in terms of switching losses versus power delivered to load 112. The transition switching strategy 204 is even less efficient than the constant period switching strategy 302.